Contents Menu Expand Light mode Dark mode Auto light/dark, in light mode Auto light/dark, in dark mode Skip to content
FABulous: An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️ v0.1.dev105+g6d33ce6d8
Logo
FABulous An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️ v0.1
  • Getting Started
    • Quick start
    • Using FABulous in GitHub Codespaces
    • Installation Method
      • uv based setup
      • venv based setup
      • Install Required CAD tools
      • docker based setup
      • Nix-based Development Environment
  • User Guide
    • Building your eFPGA
      • Fabric definition
      • Building fabric
      • FABulous Fabric Automation
      • Convert your design into GDSII format
      • Timing Characterization
      • GDS Flow Configuration Variables
    • CLI Usage Guide
      • FABulous CLI — Features and Usage
      • Interactive CLI Commands Reference
      • FABulous Configuration Variables
    • Using the eFPGA
      • Synthesis
        • Yosys models
        • Yosys compilation
      • Place and Route
        • Nextpnr models
        • Nextpnr compilation
      • FASM to Bitstream
    • Simulation and emulation
      • Simulation setup
      • Emulation setup
  • Development
  • Chip Gallery
  • Team and Contact
  • Publications
  • API Reference
    • fabulous
      • custom_exception
      • fabric_cad
        • gen_bitstream_spec
        • gen_design_top_wrapper
        • gen_npnr_model
        • timing_model
          • FABulous_timing_model
          • FABulous_timing_model_interface
          • hdlnx
            • hdlnx_timing_model
            • sdfnx
              • sdf_to_graph
              • sdf_to_graph_base
              • timing_graph
            • verilog_gate_level
          • models
          • tools
            • specification
            • sta_tools
              • opensta
            • synth_tools
              • yosys
      • fabric_definition
        • bel
        • configmem
        • define
        • fabric
        • gen_io
        • port
        • supertile
        • tile
        • wire
        • yosys_obj
      • fabric_generator
        • code_generator
          • code_generator
          • code_generator_VHDL
          • code_generator_Verilog
        • gds_generator
          • flows
            • fabric_macro_flow
            • flow_define
            • full_fabric_flow
            • tile_macro_flow
          • gen_io_pin_config_yaml
          • helper
          • script
            • fabric_io_place
            • odb_power
            • odb_protocol
            • tile_io_place
          • steps
            • add_buffer
            • auto_diode
            • condition_magic_drc
            • custom_pdn
            • extract_pdk_info
            • fabric_IO_placement
            • global_tile_opitmisation
            • odb_connect_pdn
            • round_die_area
            • tile_IO_placement
            • tile_optimisation
            • while_step
        • gen_fabric
          • fabric_automation
          • gen_configmem
          • gen_fabric
          • gen_helper
          • gen_switchmatrix
          • gen_tile
          • gen_top_wrapper
        • parser
          • parse_configmem
          • parse_csv
          • parse_hdl
          • parse_switchmatrix
      • fabulous
      • fabulous_api
      • fabulous_cli
        • cmd_synthesis
        • fabulous_cli
        • helper
      • fabulous_settings
      • geometry_generator
        • bel_geometry
        • fabric_geometry
        • geometry_gen
        • geometry_obj
        • port_geometry
        • sm_geometry
        • tile_geometry
        • wire_geometry
      • processpool
Back to top
View this page
Edit this page

Team and Contact¶

FABulous is maintained by Professor Dirk Koch’s research groups at the University of Manchester and the University of Heidelberg.

Next
Publications
Previous
Chip Gallery
Copyright © 2021, University of Manchester
Made with Sphinx and @pradyunsg's Furo