yosys

Yosys Tool Interface, which uses Yosys to synthesize a Verilog design.

Converts a gate-level netlist and then uses an STA tool (e.g., OpenSTA) to analyze the netlist and generate an SDF file.

The SDF file is then parsed to create a timing graph representation of the design. This module provides a high-level interface for performing synthesis and timing analysis using Yosys.

Classes

YosysTool

YosysTool is a synthesis tool interface that uses Yosys.

Module Contents

YosysTool

class YosysTool(synth_executable, top_name=None, is_gate_level=False, techmap_files=None, tiehi_cell_and_port=None, tielo_cell_and_port=None, min_buf_cell_and_ports=None, verilog_files=None, liberty_files=None, debug=False, flat=False)

Bases: SynthTool

YosysTool is a synthesis tool interface that uses Yosys.

It will synthesize Verilog RTL into a gate-level netlist.

It supports various synthesis options such as techmapping, tie-high/low cell mapping, and buffer insertion. The generated gate-level netlist can then be used for static timing analysis (STA) with tools like OpenSTA.

Initializes the YosysTool with the given configuration parameters.

Parameters:

• synth_executable (Path | str) – The path to the Yosys executable.

• top_name (str | None) – The name of the top-level module in the Verilog design.

• is_gate_level (bool) – Flag indicating whether the input Verilog files are already gate-level netlists (True) or need to be synthesized (False).

• techmap_files (list[Path] | None) – List of techmap files for Yosys or None if not using techmapping.

• tiehi_cell_and_port (str | None) – String specifying the tie-high cell and port for Yosys hilomap, or None if not using hilomap.

• tielo_cell_and_port (str | None) – String specifying the tie-low cell and port for Yosys hilomap, or None if not using hilomap.

• min_buf_cell_and_ports (str | None) – String specifying the minimum buffer cell and ports for Yosys insbuf, or None if not using insbuf.

• verilog_files (list[Path] | Path | None) – List of Verilog RTL files or a single Verilog RTL file to be synthesized.

• liberty_files (list[Path] | Path | None) – List of Liberty files or a single Liberty file for the target technology.

• debug (bool) – Flag indicating whether to enable debug mode for verbose output during synthesis.

• flat (bool) – Flag indicating whether to flatten the hierarchy during synthesis (default: False).

Properties

property synth_design_name: str

Return the name of the design being synthesized.

property synth_liberty_files: list[Path] | Path

Return the list of Liberty files used for synthesis.

property synth_netlist_file: Path

Return the path to the generated gate-level netlist file.

Raises:

RuntimeError – If the netlist file has not been generated yet ” “(i.e., synthesize() has not been called).

property synth_passthrough: bool

Return whether the synthesis tool is in passthrough mode.

(i.e., it does not perform actual synthesis but simply passes through the input rtl files).

property synth_rtl_files: list[Path] | Path

Return the list of RTL Verilog files used for synthesis.

Methods

synth_clean_up() → None

Clean up the temporary gate-level netlist file generated by Yosys.

synth_synthesize() → None

Generate a temporary gate-level netlist from the Verilog RTL files.

It uses Yosys. The gate-level netlist is created in a temporary location and deleted after use.

Returns:

If netlist provided is already gate-level.

Raises:

RuntimeError – If synthesis fails or if the generated netlist file is empty or not created.