port

Port definition module for FPGA fabric.

This module contains the Port class, which represents a connection point on a tile in the FPGA fabric. Ports define the physical and logical characteristics of wires entering or leaving a tile, including their direction, source and destination names, offsets, and wire counts. These definitions are typically parsed from a CSV file that describes the fabric architecture.

Classes

Port	Store all the port information defined in the CSV file.

Module Contents

Port

class Port

Store all the port information defined in the CSV file.

The name, inOut and sideOfTile are added attributes to aid the generation of the fabric.

The name and inOut are related. If the inOut is INPUT, then the name is the source name of the port on the tile. Otherwise, the name is the destination name of the port on the tile.

The sideOfTile defines where the port is physically located on the tile, since for a north direction wire, the input will be physically located on the south side of the tile. The sideOfTile will make determining where the port is located much easier.

Variables:

• wireDirection (Direction) – The direction attribute in the CSV file

• sourceName (str) – The source_name attribute in the CSV file

• xOffset (int) – The X-offset attribute in the CSV file

• yOffset (int) – The Y-offset attribute in the CSV file

• destinationName (str) – The destination_name attribute in the CSV file

• wireCount (int) – The wires attribute in the CSV file

• name (str) – The name of the port

• inOut (IO) – The IO direction of the port

• sideOfTile (Side) – The side on which the port is physically located in the tile

Methods

expandPortInfo(mode='SwitchMatrix') → tuple[list[str], list[str]]

Expand the port information to the individual bit signal.

If ‘Indexed’ is in the mode, then brackets are added to the signal name.

Parameters:

mode (str, optional) – Mode for expansion. Defaults to “SwitchMatrix”. Possible modes are ‘all’, ‘allIndexed’, ‘Top’, ‘TopIndexed’, ‘AutoTop’, ‘AutoTopIndexed’, ‘SwitchMatrix’, ‘SwitchMatrixIndexed’, ‘AutoSwitchMatrix’, ‘AutoSwitchMatrixIndexed’

Returns:

A tuple of two lists. The first list contains the source names of the ports and the second list contains the destination names of the ports.

expandPortInfoByName(indexed=False, prefix='', escape=False) → list[str]

Expand port information to individual wire names.

Generates a list of individual wire names for this port, accounting for wire count and offset calculations. For termination ports (NULL), the wire count is multiplied by the Manhattan distance.

Parameters:

• indexed (bool, optional) – If True, wire names use bracket notation (e.g., port[0]). If False, wire names use simple concatenation (e.g., port0). Defaults to False.

• prefix (str, optional) – A prefix to prepend to the port name, by default “”.

• escape (bool, optional) – If True, escape special characters in the port names (e.g., for regex), by default False.

Returns:

List of individual wire names for this port.

expandPortInfoByNameTop(indexed=False, prefix='', escape=False) → list[str]

Expand port information for top-level connections.

Similar to expandPortInfoByName but specifically for top-level tile connections. The start index is calculated differently to handle the top slice of wires for routing fabric connections.

Parameters:

• indexed (bool, optional) – If True, wire names use bracket notation (e.g., port[0]). If False, wire names use simple concatenation (e.g., port0). Defaults to False.

• prefix (str, optional) – A prefix to prepend to the port name, by default “”.

• escape (bool, optional) – If True, escape special characters in the port names (e.g., for regex), by default False.

Returns:

List of individual wire names for top-level connections.

getPortRegex(indexed=False, prefix='') → str

Expand port information to individual wire names.

Generates a regex expression for this port, accounting for wire count and offset calculations.

Parameters:

• indexed (bool, optional) – If True, wire names use bracket notation (e.g., port[0]). If False, wire names use simple concatenation (e.g., port0). Defaults to False.

• prefix (str, optional) – A prefix to prepend to the port name, by default “”.

Returns:

A regex expression matching the port’s wire names.