hdlnx_timing_model¶

Convertes verilog RTL into a verilog gate-level netlist.

Will use an external synthesis tool.

In this context a sysnthesis tool can be anything that can convert RTL verilog into gate-level verilog, that means also tools that can do backend design steps like technology mapping and place&route.

It then uses the VerilogGateLevelTimingGraph class to generate a timing graph from the gate-level netlist.

Classes¶

HdlnxTimingModel

Class to generate a timing graph from Verilog RTL.

Module Contents¶

HdlnxTimingModel¶

class HdlnxTimingModel(sta_tool, synth_tool, delay_type_str=DelayType.MAX_ALL, debug=False)[source]¶

Bases: VerilogGateLevelTimingGraph

Class to generate a timing graph from Verilog RTL.

It does this by first synthesizing the RTL into a gate-level netlist using an external synthesis tool, and then using the VerilogGateLevelTimingGraph class to generate the timing graph.

Initializes the HdlnxTimingModel with the given synthesis and STA tools, and generates the timing graph.

Parameters:

sta_tool (StaTool) – The static timing analysis tool to use for generating the timing graph.
synth_tool (SynthTool) – The synthesis tool to use for converting RTL to gate-level netlist.
delay_type_str (DelayType, optional) – The type of delay to use for the timing graph (default is DelayType.MAX_ALL).
debug (bool, optional) – If True, print debug warnings about overwriting STA tool configurations (default is False).