yosys_obj¶

Object representation of the Yosys Json file.

Attributes¶

`BitVector`
`KeyValue`

Classes¶

`YosysCellDetails`	Represents a cell instance in a Yosys module.
`YosysJson`	Root object representing a complete Yosys JSON file.
`YosysMemoryDetails`	Represents memory block details in a Yosys module.
`YosysModule`	Represents a module in a Yosys design.
`YosysNetDetails`	Represents net/wire details in a Yosys module.
`YosysPortDetails`	Represents port details in a Yosys module.

Module Contents¶

BitVector[source]¶

KeyValue[source]¶

YosysCellDetails¶

class YosysCellDetails[source]¶

Represents a cell instance in a Yosys module.

Cells are instantiated components like logic gates, flip-flops, or user-defined modules.

Variables:

hide_name (Literal[1, 0]) – Whether to hide the cell name in output (1=hide, 0=show).
type (str) – Cell type/primitive name (e.g., “AND”, “DFF”, custom module name).
parameters (KeyValue) – Cell parameters as string key-value pairs.
attributes (KeyValue) – Cell attributes including metadata and synthesis directives.
connections (dict[str, BitVector]) – Port connections mapping port names to bit vectors.
port_directions (dict[str, Literal["input", "output", "inout"]], optional) – Direction of each port. Default is empty dict.
model (str, optional) – Associated model name. Default is “”.

YosysJson¶

class YosysJson(path)[source]¶

Root object representing a complete Yosys JSON file.

Load and parse a HDL file to a Yosys JSON object.

This class provides the main interface for loading and analyzing Yosys JSON netlists. It contains all modules in the design and provides utility methods for common netlist analysis tasks.

Parameters:

path (Path) – Path to a HDL file.

Variables:

srcPath (Path) – Path to the source JSON file.
creator (str) – Tool that created the JSON (usually “Yosys”).
modules (dict[str, YosysModule]) – Dictionary mapping module names to YosysModule objects.
models (dict) – Dictionary of behavioral models (implementation-specific).

Raises:

FileNotFoundError – If the JSON file doesn’t exist.
InvalidFileType – If the file type is not .vhd, .vhdl, .v, or .sv.
RuntimeError – If Yosys or GHDL fails to process the file.
ValueError – If there is a miss match in the VHDL entity and the Yosys top module.

Methods¶

getNetPortSrcSinks(net) → tuple[tuple[str, str], list[tuple[str, str]]][source]¶

Find the source and sink connections for a given net.

This method analyzes the netlist to determine what drives a net (source) and what it connects to (sinks).

Parameters:

net (int) – Net ID to analyze.

Returns:

A tuple containing:

Source: (cell_name, port_name) tuple for the driving cell/port
Sinks: List of (cell_name, port_name) tuples for driven cells/ports

Raises:

ValueError – If net is not found or has multiple drivers.

Notes

If no driver is found, the source will be (“”, “z”) indicating a high-impedance or undriven net.

getTopModule() → tuple[str, YosysModule][source]¶

Find and return the top-level module in the design.

The top module is identified by having a “top” attribute. If no “top” module is found, falls back to the first module with a “blackbox” attribute (e.g. for BEL definitions that only contain a blackbox module).

Returns:

A tuple containing:

The name of the top-level module (str)
The YosysModule object for the top-level module

Raises:

ValueError – If no top or blackbox module is found in the design.

isTopModuleNet(net) → bool[source]¶

Check if a net ID corresponds to a top-level module port.

Parameters:: net (int) – Net ID to check.
Returns:: True if the net is connected to a top module port, False otherwise.

YosysMemoryDetails¶

class YosysMemoryDetails[source]¶

Represents memory block details in a Yosys module.

Memory blocks are inferred or explicitly instantiated memory elements.

Variables:

hide_name (Literal[1, 0]) – Whether to hide the memory name in output (1=hide, 0=show).
attributes (KeyValue) – Memory attributes and metadata.
width (int) – Data width in bits.
start_offset (int) – Starting address offset.
size (int) – Memory size (number of addressable locations).

YosysModule¶

class YosysModule(*, attributes, parameter_default_values, ports, cells, memories, netnames)[source]¶

Represents a module in a Yosys design.

A module contains the structural description of a digital circuit including its interface (ports), internal components (cells), memory blocks, and interconnections (nets).

Parameters:

attributes (KeyValue) – Module attributes dictionary.
parameter_default_values (KeyValue) – Parameter defaults dictionary.
ports (dict[str, YosysPortDetails]) – Ports dictionary (will be converted to YosysPortDetails objects).
cells (dict[str, YosysCellDetails]) – Cells dictionary (will be converted to YosysCellDetails objects).
memories (dict[str, YosysMemoryDetails]) – Memories dictionary (will be converted to YosysMemoryDetails objects).
netnames (dict[str, YosysNetDetails]) – Netnames dictionary (will be converted to YosysNetDetails objects).

Variables:

attributes (KeyValue) – Module attributes and metadata (e.g., “top” for top module).
parameter_default_values (KeyValue) – Default values for module parameters.
ports (dict[str, YosysPortDetails]) – Dictionary mapping port names to YosysPortDetails.
cells (dict[str, YosysCellDetails]) – Dictionary mapping cell names to YosysCellDetails.
memories (dict[str, YosysMemoryDetails]) – Dictionary mapping memory names to YosysMemoryDetails.
netnames (dict[str, YosysNetDetails]) – Dictionary mapping net names to YosysNetDetails.

YosysNetDetails¶

class YosysNetDetails[source]¶

Represents net/wire details in a Yosys module.

Nets are the connections between cells and ports in the design.

Variables:

hide_name (Literal[1, 0]) – Whether to hide the net name in output (1=hide, 0=show).
bits (BitVector) – Bit vector representing the net’s signals.
attributes (KeyValue) – Net attributes including unused bit information.
offset (int) – Bit offset for multi-bit nets.
upto (int) – Upper bound for bit ranges.
signed (int) – Whether the net is signed (0=unsigned, 1=signed).

YosysPortDetails¶

class YosysPortDetails[source]¶

Represents port details in a Yosys module.

Variables:

direction (Literal["input", "output", "inout"]) – Port direction.
bits (BitVector) – Bit vector representing the port’s signals.
offset (int) – Bit offset for multi-bit ports.
upto (int) – Upper bound for bit ranges.
signed (int) – Whether the port is signed (0=unsigned, 1=signed).