tile_geometry¶
Tile geometry generation and management for FABulous FPGA tiles.
This module provides the TileGeometry class for representing and generating the
geometric layout of FPGA tiles, including switch matrices, BELs, and interconnect wires.
It handles both direct connections to neighboring tiles and complex stair-like routing
for longer-distance connections.
Classes¶
A data structure representing the geometry of a tile. |
Module Contents¶
TileGeometry¶
- class TileGeometry[source]¶
A data structure representing the geometry of a tile.
Initializes all attributes to default values: empty name, zero dimensions, no border, and empty lists for geometric components.
- Variables:
name (str) – Name of the tile
width (int) – Width of the tile
height (int) – Height of the tile
border (Border) – Border of the fabric the tile is on
wireConstraints (WireConstraints) – Wire constraints of the tile
neighbourConstraints (WireConstraints | None) – Wire constraints of neighbouring tiles
smGeometry (SmGeometry) – Geometry of the tiles switch matrix
belGeomList (list[BelGeometry]) – List of the geometries of the tiles bels
wireGeomList (list[WireGeometry]) – List of the geometries of the tiles wires
stairWiresList (list[StairWires]) – List of the stair-like wires of the tile
stairWireOffset (int) – Offset for stair wires, relative to regular wires Should be relatively small, to prevent generating stair wires overlapping with regular wires.
currPortGroupId (int) – Current port group ID being processed
queuedAdjustmentBottom (int) – Queued adjustment for bottom positioning
queuedAdjustmentLeft (int) – Queued adjustment for left positioning
reserveStairSpaceBottom (bool) – Whether to reserve space at bottom for stair wires
reserveStairSpaceLeft (bool) – Whether to reserve space at left for stair wires
eastMiddleY (int) – Middle Y coordinate for east side
northMiddleX (int) – Middle X coordinate for north side
southMiddleX (int) – Middle X coordinate for south side
westMiddleY (int) – Middle Y coordinate for west side
Methods¶
- adjustDimensions(maxWidthInColumn, maxHeightInRow, maxSmWidthInColumn, maxSmRelXInColumn) None[source]¶
Adjust tile dimensions to match maximum values in fabric grid.
Normalizes the tile dimensions and switch matrix positioning to align with the maximum dimensions found in the same fabric column/row, ensuring uniform tile sizing across the fabric.
- Parameters:
- adjustSmPos(lowestSmYInRow, padding) None[source]¶
Ajusts the position of the switch matrix.
This is done by using the lowest Y coordinate of any switch matrix in the same row for reference.
After this step is completed for all switch matrices, their southern edge will be on the same Y coordinate, allowing for easier inter-tile routing.
- generateDirectWires(padding) None[source]¶
Generate wires to neighbouring tiles, which are straightforward to generate.
- Parameters:
padding (int) – The padding value to use for wire generation
- Raises:
InvalidPortType – If a port with offset 1 has no tile side defined
- generateGeometry(tile, padding) None[source]¶
Generate the geometry for a tile.
Creates geometric representations for all BELs and the switch matrix, then calculates the overall tile dimensions based on the generated components and padding requirements.
- generateIndirectWires() None[source]¶
Generate wires to non-neighbouring tiles.
These wires require staircase-like routing patterns to reach tiles that are not direct neighbors (offset >= 2). The routing varies by tile side and wire direction.
- Raises:
InvalidPortType – If a port has abs(offset) > 1 but no tile side assigned.
- generateWires(padding) None[source]¶
Generate all wire geometries for the tile.
Creates wire geometries for BEL connections, direct connections to neighboring tiles, and indirect connections requiring stair-like routing. Ensures proper alignment of wire positions across different tile types.
- Parameters:
padding (int) – The padding space to add around wire routing
- indirectEastSideWire(portGeom) None[source]¶
Generate indirect wires on the east side of the tile with stair-like routing.
Creates staircase-shaped wire routing for connections that span multiple tiles eastward. Manages stair wire generation and space reservation based on wire direction and grouping.
- Parameters:
portGeom (PortGeometry) – The port geometry defining the wire characteristics
- indirectNorthSideWire(portGeom) None[source]¶
Generate indirect wires with stair-like routing.
Creates staircase-shaped wire routing for connections that span multiple tiles northward. Manages stair wire generation and space reservation based on wire direction and grouping.
- Parameters:
portGeom (PortGeometry) – The port geometry defining the wire characteristics
- indirectSouthSideWire(portGeom) None[source]¶
Generate indirect wires on the south side without creating stair-like wires.
Creates L-shaped wire routing for southward connections. Unlike north side wires, this method only generates the connection wires and reserves space for stair wires created by the north side method.
- Parameters:
portGeom (PortGeometry) – The port geometry defining the wire characteristics
- indirectWestSideWire(portGeom) None[source]¶
Generate indirect wires on the west side without creating stair-like wires.
Creates L-shaped wire routing for westward connections. Unlike east side wires, this method only generates the connection wires and reserves space for stair wires created by the east side method.
- Parameters:
portGeom (PortGeometry) – The port geometry defining the wire characteristics
- saveToCSV(writer) None[source]¶
Save tile geometry data to CSV format.
Writes the tile geometry information including dimensions and all geometric components (switch matrix, BELs, wires, stair wires) to a CSV file using the provided writer.
- Parameters:
writer (csvWriter) – The CSV writer object to use for output