gen_switchmatrixΒΆ
Switch matrix generation module for FABulous FPGA tiles.
This module generates RTL code for configurable switch matrices within FPGA tiles. Switch matrices handle the routing of signals between tile ports, BEL inputs/outputs, and jump wires. The module supports various configuration modes and multiplexer styles.
Key features:
CSV and list file parsing for switch matrix configurations
Support for custom and generic multiplexer implementations
Configuration bit calculation and management
Debug signal generation for switch matrix analysis
Multiple configuration modes (FlipFlop chain, Frame-based)
FunctionsΒΆ
|
Generate the RTL code for the tile switch matrix. |
Module ContentsΒΆ
- genTileSwitchMatrix(writer, fabric, tile, switch_matrix_debug_signal, csv_output_dir=None) None[source]ΒΆ
Generate the RTL code for the tile switch matrix.
The switch matrix generated will be based on the
matrixDirattribute of the tile. If the given file format is.csv, it will be parsed as a switch matrix.csvfile. If the given file format is.list, the tool will convert the.listfile into a switch matrix with specific ordering first before progressing. If the given file format is Verilog or VHDL, then the function will not generate anything.- Parameters:
writer (CodeGenerator) β The code generator instance for RTL output
fabric (Fabric) β The fabric object containing global configuration
tile (Tile) β The tile object containing BELs and port information
switch_matrix_debug_signal (bool) β Whether to generate debug signals for the switch matrix.
csv_output_dir (Path | None) β Optional directory to write the generated CSV file when converting from
.listformat. If None, the CSV is written to the same directory as the source.listfile. This parameter is ignored when the input is already a.csvfile.
- Raises:
InvalidFileType β If
matrixDirdoes not contain a valid file format.ValueError β If any port in the switch matrix is not connected to anything.