opensta¶
OpenSTA Tool Interface.
Provides an interface to run OpenSTA for static timing analysis on a given Verilog netlist.
Classes¶
OpenSTA is an open-source static timing analysis tool. |
Module Contents¶
OpenStaTool¶
- class OpenStaTool(sta_executable, liberty_files=None, top_name=None, verilog_netlist=None, spef_files=None, debug=False)[source]¶
Bases:
StaToolOpenSTA is an open-source static timing analysis tool.
Initializes the OpenSTATool with the given parameters.
This class provides an interface to run OpenSTA on a given netlist, and to retrieve the generated SDF file after analysis.
- Parameters:
sta_executable (Path | str) – The path to the OpenSTA executable.
liberty_files (list[Path] | Path | None) – The Liberty timing model file(s) to use for analysis. Can be a single Path or a list of Paths.
top_name (str | None) – The name of the top-level design to analyze.
verilog_netlist (Path | None) – The path to the Verilog gate-level netlist to analyze. If None, it must be set before calling analyze().
spef_files (list[Path] | Path | None) – The SPEF RC extraction file(s) to use for analysis. Can be a single Path or a list of Paths.
debug (bool) – Flag to enable debug mode, which will print additional information during analysis. Default is False.
Properties¶
- property sta_liberty_files: list[Path] | Path | None[source]¶
Return the list of Liberty files used for STA analysis.
- property sta_rc_files: list[Path] | Path | None[source]¶
Return the list of RC files used for STA analysis.
- property sta_sdf_file: Path[source]¶
Return the path to the generated SDF file after analysis.
- Raises:
RuntimeError – If the SDF file has not been generated yet.
Methods¶
- sta_analyze() None[source]¶
Generate an temporary SDF file from the Verilog gate-level netlist.
Uses OpenSTA. The SDF file is created in a temporary location and deleted after use.
- Raises:
RuntimeError – If the SDF file cannot be generated or is empty after running OpenSTA.