FABulous_timing_model¶
Defines the FABulousTileTimingModel class.
It is responsible for extracting timing information for a specific tile in the FABulous project.
It reads the project files, initializes synthesis-level and physical-level timing models using the HdlnxTimingModel class, and provides methods to calculate delays for internal and external PIPs (Programmable Interconnect Points) using either structural or physical approaches.
Classes¶
Reads the FABulous project files and extracts timing information. |
Module Contents¶
FABulousTileTimingModel¶
- class FABulousTileTimingModel(config, fabric, tile_name=None)[source]¶
Reads the FABulous project files and extracts timing information.
Initializes the FABulousTileTimingModel with the given configuration and fabric definition. The configuration object must match the TimingModelConfig schema defined in the models module.
It initializes both synthesis-level and physical-level timing models using the HdlnxTimingModel class.
It provides methods to calculate delays for internal PIPs (within the switch matrix) and external PIPs (between the tile and the next tile) using either structural or physical approaches.
Supported synthesis tools:
Yosys, keyword: “yosys”
Supported static timing analysis (STA) tools:
OpenSTA, keyword: “opensta”
- Parameters:
config (TimingModelConfig) – Configuration object for the timing model.
fabric (Fabric) – The FABulous fabric object.
tile_name (str | None) – The name of the tile for which the timing model is being created.
Methods¶
- external_pip_delay(pip_src, pip_dst) float[source]¶
Choose the method to calculate external PIP delay based on the mode.
(physical or structural).
- external_pip_delay_physical(pip_src, pip_dst) float[source]¶
Calculate delay for external PIPs between the tile and the next tile.
Physical approach. It is Tile to Tile, Tile port to SWM, SWM to SWM, SWM output to tile port. This method uses the physical-level timing model to provide more accurate delay estimates by considering the actual physical implementation. For tile interconnects, we assume a stitched connection with a fixed small delay.
- external_pip_delay_structural(pip_src, pip_dst) float[source]¶
Calculate delay for external PIPs between the tile and the next tile.
Structural approach. It is Tile to Tile, Tile port to SWM, SWM to SWM, SWM output to tile port.
- internal_pip_delay(pip_src, pip_dst) float[source]¶
Choose the method to calculate internal PIP delay based on the mode.
(physical or structural).
- internal_pip_delay_physical(pip_src, pip_dst) float[source]¶
Calculate delay between two PIPs using physical design information.
This method uses the physical-level timing model to provide more accurate delay estimates by considering the actual physical implementation.
Synthesis-level resolution (extract the realted module ports that are connected to the SMW mux to which the PIP belongs)
Physical-level resolution map the synthesis-level top-level ports that are related to the swm mux to physical-level swm mux pins to find the sm mux output pin (Then we can calc the delay between pip_src and pip_dst). To find the swm mux output we will use a method that we call earliest node convergence. That means for MUX the topology we know that all inputs converge to the output pin (mostly), so we can find the earliest common node from all the input ports found above. Similar to graph betweenness centrality subset, but here we want to find the node that minimizes the maximum distance from all the input ports.
- internal_pip_delay_structural(pip_src, pip_dst) float[source]¶
Calculate delay between two PIPs in the switch matrix.
It is the fast variant that does not need physical design information, but the results may be less accurate.