specification

Define the abstract base classes for synthesis STA tool backends.

These classes specify the required methods that any concrete implementation of a synthesis or STA tool must provide, such as synthesizing a Verilog file, returning the path to the generated netlist or SDF file, and cleaning up temporary files after analysis.

Classes

StaTool	Abstract base class for static timing analysis (STA) tool backends.
SynthTool	Abstract base class for synthesis tool backends.

Module Contents

StaTool

class StaTool

Bases: ABC

Abstract base class for static timing analysis (STA) tool backends.

Concrete implementations run a timing analysis on a synthesized netlist and produce an SDF file for back-annotated simulation or further timing checks.

Properties

property sta_design_name: str

Abstractmethod:

Return the name of the design being analyzed.

property sta_liberty_files: list[Path] | Path

Abstractmethod:

Return the list of Liberty files used for STA analysis.

property sta_netlist_file: Path

Abstractmethod:

Return the path to the netlist file used for STA analysis.

property sta_rc_files: list[Path] | Path | None

Abstractmethod:

Return the list of RC files used for STA analysis.

if no RC files are specified.

property sta_sdf_file: Path

Abstractmethod:

Return the path to the generated SDF file.

Methods

abstractmethod sta_analyze() → None

Analyze the given netlist file.

abstractmethod sta_clean_up() → None

Clean up any temporary files generated during STA analysis.

SynthTool

class SynthTool

Bases: ABC

Abstract base class for synthesis tool backends.

Concrete implementations synthesize one or more RTL Verilog files into a gate-level netlist using a set of Liberty timing libraries. Implementations may optionally support a passthrough mode where the input RTL is forwarded without running synthesis.

Properties

property synth_design_name: str

Abstractmethod:

Get the name of the design being synthesized.

property synth_liberty_files: list[Path] | Path

Abstractmethod:

Return the list of Liberty files used for synthesis.

property synth_netlist_file: Path

Abstractmethod:

Return the path to the synthesized netlist file.

property synth_passthrough: bool

Abstractmethod:

Return whether the synthesis tool is in passthrough mode.

(i.e., it does not perform actual synthesis but simply passes through the input rtl files).

False otherwise.

property synth_rtl_files: list[Path] | Path

Abstractmethod:

Return the list of RTL files used for synthesis.

Methods

abstractmethod synth_clean_up() → None

Clean up any temporary files generated during synthesis.

abstractmethod synth_synthesize() → None

Synthesize the given Verilog file.