models¶

Models for the SDF timing model generation and analysis.

This module defines the data models used for representing the SDF timing graph, components, and configuration for the timing model generation process. It includes enumerations for cell types, delay types, timing model modes, synthesis and STA tools, as well as dataclasses and Pydantic models for components, the SDF graph object, and the timing model configuration. These models provide a structured way to represent the timing information extracted from SDF files and the configuration parameters for generating timing models, allowing for easier manipulation and analysis of the timing data throughout the processing pipeline.

Classes¶

`Component`	Represents a component in the SDF timing model.
`DelayType`	Enumeration of delay types for the SDF timing model.
`InternalPipCacheEntry`	Represents a cache entry for the internal pip delay calculation.
`SDFCellType`	Enumeration of cell types for the SDF timing model.
`SDFGobject`	Represents the SDF timing graph object.
`TimingModelConfig`	Configuration class for the SDF timing model.
`TimingModelMode`	Enumeration of timing model modes for the SDF timing model.
`TimingModelStaTools`	Enumeration of static STA tools configured for the timing model.
`TimingModelSynthTools`	Enumeration of synthesis tools configured for the timing model.
`TimingModelTileSourceFiles`	Configuration class for the source files related to a specific tile.

Module Contents¶

Component¶

class Component[source]¶

Represents a component in the SDF timing model.

Its either an INTERCONNECT or an IOPATH for the timing graph. But it can also be: REMOVAL, RECOVERY, SETUP, HOLD, WIDTH.

Variables:

c_type (SDFCellType) – Type of the component, either “INTERCONNECT” or “IOPATH” for the timing graph. Other types include: “REMOVAL”, “RECOVERY”, “SETUP”, “HOLD”, “WIDTH”.
connection_string (str) – Unique identifier for the component.
cell_name (str) – Name of the cell e.g., ‘AND2X1’.
from_cell_instance (str) – Instance name of the source cell.
to_cell_instance (str) – Instance name of the destination cell.
from_cell_pin (str) – Pin name on the source cell.
to_cell_pin (str) – Pin name on the destination cell.
delay (float) – Delay associated with this component: INTERCONNECT delay: cell to cell delay, IOPATH delay: pin to pin delay within a cell. Is a single delay over fast, slow (min, max) by using a cost function to combine them.
delay_paths (dict) – Dictionary containing detailed delay paths information.
is_one_cell_instance (bool) – True if from_cell_instance and to_cell_instance are the same.
is_timing_check (bool) – True if the component represents a timing check.
is_timing_env (bool) – True if the component represents a timing environment.
is_absolute (bool) – True if the delay is absolute.
is_incremental (bool) – True if the delay is incremental.
is_cond (bool) – True if the delay is conditional.
cond_equation (str) – Condition equation if is_cond is True.
from_pin_edge (str) – Edge type for the from pin, e.g., “posedge” or “negedge”.
to_pin_edge (str) – Edge type for the to pin, e.g., “posedge” or “negedge”.

DelayType¶

class DelayType[source]¶

Bases: StrEnum

Enumeration of delay types for the SDF timing model.

Includes various combinations of min, max, avg, fast, and slow delays.

Variables:

MIN_ALL – Represents the minimum delay across all conditions.
MAX_ALL – Represents the maximum delay across all conditions.
AVG_ALL – Represents the average delay across all conditions.
AVG_FAST – Represents the average delay under fast conditions.
AVG_SLOW – Represents the average delay under slow conditions.
MAX_FAST – Represents the maximum delay under fast conditions.
MAX_SLOW – Represents the maximum delay under slow conditions.
MIN_FAST – Represents the minimum delay under fast conditions.
MIN_SLOW – Represents the minimum delay under slow conditions.
signature. (Initialize self. See help(type(self)) for accurate)

InternalPipCacheEntry¶

class InternalPipCacheEntry[source]¶

Represents a cache entry for the internal pip delay calculation.

Contains all relevant information for the calculation, including the source pip, destination pip, the best path through the switch matrix, the nearest ports to the source and destination pips, the reference output port for convergence, and the physical output of the switch matrix.

Variables:

begin_pip (str) – The begin pip for the internal pip delay calculation.
swm_mux_for_pips (list[str]) – The list of switch matrix multiplexers (swm mux) that are relevant for the source and destination pips.
swm_nearest_ports_in (tuple[dict[str, list[str]], list[str]] | None) –
A tuple containing two elements:
- A dictionary mapping each pip of a swm mux (source and destination) to a list of its nearest input ports.
- A list of all nearest input ports for both source and destination pips of a swm mux.
swm_nearest_ports_out (tuple[dict[str, list[str]], list[str]] | None) –
A tuple containing two elements:
- A dictionary mapping each pip of a swm mux (source and destination) to a list of its nearest output ports.
- A list of all nearest output ports for both source and destination pips of a swm mux.
swm_output_pin (tuple[list[str], float | None, dict[str, dict[str, float]]] | None) –
A tuple containing three elements:
- A list of output pin(s) of the swm mux that were found during convergence detection.
- The best cost associated with the best convergence node.
- A dictionary mapping source -> node -> distance.
swm_mux_resolved (dict[str, list[str]] | None) – A dictionary mapping each pip of a swm mux (source and destination) to a list of resolved pins for the swm mux instance to cell pins.

SDFCellType¶

class SDFCellType[source]¶

Bases: StrEnum

Enumeration of cell types for the SDF timing model.

Includes INTERCONNECT and IOPATH for the timing graph, as well as other types like REMOVAL, RECOVERY, SETUP, HOLD, WIDTH.

Variables:

IOPATH – Represents an IOPATH component, which defines timing paths between pins within the same cell.
INTERCONNECT – Represents an INTERCONNECT component, which defines timing paths between pins across different cells (i.e., inter-cell connections).
REMOVAL – Represents a REMOVAL component, which defines timing checks for signal removal.
RECOVERY – Represents a RECOVERY component, which defines timing checks for signal recovery.
SETUP – Represents a SETUP component, which defines timing checks for setup time.
HOLD – Represents a HOLD component, which defines timing checks for hold time.
WIDTH – Represents a WIDTH component, which defines timing checks for pulse width.
signature. (Initialize self. See help(type(self)) for accurate)

SDFGobject¶

class SDFGobject[source]¶

Represents the SDF timing graph object.

Contains the directed graph representation of the timing model, as well as associated metadata such as header information, SDF data dictionary parsed from the file, cell names, instances, IOPATHs, and interconnects.

Variables:

nx_graph (nx.DiGraph) – The directed graph representation of the timing model, where nodes represent pins and edges represent timing paths with associated delay information.
hier_sep (str) – The hierarchical separator used in instance names, extracted from the SDF header information.
header_info (dict) – Dictionary containing header information from the SDF file, such as version, date, vendor, program, and hierarchical separator.
sdf_data (dict) – The full SDF data parsed from the file, including cells, instances, IOPATHs, interconnects, and timing checks.
cells (list[str]) – List of cell names defined in the SDF file.
instances (dict[str, list[Component]]) – Dictionary mapping instance names of cells to lists of Component instances representing the timing paths (IOPATHs and INTERCONNECTs) associated with each instance.
io_paths (list[Component]) – List of Component instances representing the IOPATHs defined in the SDF file, which represent timing paths between pins within the same cell.
interconnects (list[Component]) – List of Component instances representing the INTERCONNECTs defined in the SDF file, which represent timing paths between pins across different cells (i.e., inter-cell connections).

TimingModelConfig¶

class TimingModelConfig(/, **data)[source]¶

Bases: BaseModel

Configuration class for the SDF timing model.

Containins all necessary parameters and settings for generating the timing model from the SDF file.

Variables:

model_config – Pydantic configuration for the model, allowing for strict validation and assignment.
project_dir (Path) – The directory of the project, used for resolving relative paths.
liberty_files (list[Path] | Path) – The list of liberty files or a single liberty file path used for timing analysis.
min_buf_cell_and_ports (str) – The minimum buffer cell and ports “cell_name input_port output_port”.
synth_executable (Path | str) – The executable command for the synthesis tool.
sta_executable (Path | str) – The executable command for the static timing analysis tool.
pdk_name (str | None) – The name of the PDK being used, It’s just for informational purposes.
techmap_files (list[Path] | Path | None) – The list of technology mapping files or a single techmap file path or None if not applicable.
tiehi_cell_and_port (str | None) – The cell and port used for tie-high connections “cell_name port_name”, or None if not applicable.
tielo_cell_and_port (str | None) – The cell and port used for tie-low connections “cell_name port_name”, or None if not applicable.
custom_per_tile_source_files (dict[str, TimingModelTileSourceFiles] | None) – A dictionary mapping tile names to TimingModelTileSourceFiles instances containing custom source file paths, or None if not applicable. This will overwrite the default paths defined in the project directory for the specific tile.
sta_program (TimingModelStaTools) – The static timing analysis tool to be used, specified as an instance of the TimingModelStaTools enumeration.
synth_program (TimingModelSynthTools) – The synthesis tool to be used, specified as an instance of the TimingModelSynthTools enumeration.
mode (TimingModelMode) – The timing model mode to be used, specified as an instance of the TimingModelMode enumeration.
consider_wire_delay (bool) – Flag indicating whether to consider wire delay in the timing analysis.
delay_type_str (DelayType) – The type of delay to be used in the timing analysis, specified as an instance of the DelayType enumeration.
delay_scaling_factor (float) – A scaling factor to be applied to the calculated delays, allowing for adjustments based on specific requirements or to account for any discrepancies in the delay calculations. But be careful when using this, as it can lead to inaccurate timing models if not used properly.
debug (bool) – Flag to enable or disable debug mode, which may provide additional logging.
arguments. (Create a new model by parsing and validating input data from keyword)
be (Raises [ValidationError][ValidationError] if the input data cannot)
model. (validated to form a valid)
name. (self is explicitly positional-only to allow self as a field)

TimingModelMode¶

class TimingModelMode[source]¶

Bases: StrEnum

Enumeration of timing model modes for the SDF timing model.

Variables:

STRUCTURAL – Represents a structural timing model, which focuses on the interconnections and structure of the design. This mode is based on the non routed netlist and can be used if no physical post-layout netlist is available.
PHYSICAL – Represents a physical timing model, which includes detailed information about the physical layout and routing of the design. This mode is based on the routed netlist and can be used if a physical post-layout netlist is available, providing more accurate timing information that accounts for the actual physical implementation of the design.
signature. (Initialize self. See help(type(self)) for accurate)

TimingModelStaTools¶

class TimingModelStaTools[source]¶

Bases: StrEnum

Enumeration of static STA tools configured for the timing model.

Variables:

OPENSTA – Represents the OpenSTA tool, which is an open-source static timing analysis tool.
signature. (Initialize self. See help(type(self)) for accurate)

TimingModelSynthTools¶

class TimingModelSynthTools[source]¶

Bases: StrEnum

Enumeration of synthesis tools configured for the timing model.

Variables:

YOSYS – Represents the Yosys synthesis tool, which is an open-source framework for RTL synthesis.
signature. (Initialize self. See help(type(self)) for accurate)

TimingModelTileSourceFiles¶

class TimingModelTileSourceFiles(/, **data)[source]¶

Bases: BaseModel

Configuration class for the source files related to a specific tile.

Contains paths to RTL files, netlist file, and RC file.

Variables:

model_config – Pydantic configuration for the model, allowing for strict validation and assignment.
rtl_files (list[Path] | Path | None) – The list of RTL files or a single RTL file path for the tile, or None if not applicable.
netlist_file (Path | None) – The path to the netlist file for the tile, or None if not applicable.
rc_file (Path | None) – The path to the RC file for the tile, or None if not applicable.
arguments. (Create a new model by parsing and validating input data from keyword)
be (Raises [ValidationError][ValidationError] if the input data cannot)
model. (validated to form a valid)
name. (self is explicitly positional-only to allow self as a field)