verilog_gate_level

Convert a Verilog gate-level netlist into a timing graph.

It uses the SDFTimingGraph class to parse the SDF file and generate a NetworkX directed graph representing the timing relationships. It will call an external STA tool to generate the SDF file from the Verilog netlist.

Classes

VerilogGateLevelTimingGraph

Class to represent a timing graph from a Verilog gate-level netlist.

Module Contents

VerilogGateLevelTimingGraph

class VerilogGateLevelTimingGraph(top_name, sta_tool, delay_type_str=DelayType.MAX_ALL, debug=False)

Bases: SDFTimingGraph

Class to represent a timing graph from a Verilog gate-level netlist.

Initializes the VerilogGateLevelTimingGraph by generating an SDF file from the provided Verilog netlist using the specified STA tool, and then initializing the parent SDFTimingGraph with the generated SDF file.

It extends SDFTimingGraph to include functionality for generating the SDF file using an external static timing analysis (STA) tool.

Parameters:

• top_name (str) – Name of the top-level module in the Verilog netlist.

• sta_tool (StaTool) – Instance of the STA tool used for timing analysis.

• delay_type_str (DelayType, optional) – Type of delay to consider (e.g., DelayType.MAX_ALL). Default is DelayType.MAX_ALL.

• debug (bool, optional) – Flag to enable debug mode. Default is False.

Methods

find_instance_paths_by_regex(inst_regex, filter_regex=None) → list[str]

Find hierarchical instance paths matching a regex.

Parse a structural Verilog netlist, walk the hierarchy from top_module, and return all hierarchical instance paths (without the top module name) whose path matches inst_regex.

Parameters:

• inst_regex (str) – Regular expression to match hierarchical instance paths.

• filter_regex (str | None) – Optional regular expression to filter the matched instance paths.

Returns:

List of hierarchical instance paths matching the regex.

Raises:

KeyError – If the top module specified by top_name is not found in the netlist.

find_instances_paths_with_all_nets(module_name, nets, filter_regex=None) → list[str]

Find hierarchical instance paths with all nets.

Combines find_instances_with_all_nets and find_instance_paths_by_regex to return hierarchical instance paths (without top module name) for instances inside module_name that have all nets in nets connected to any of their pins.

Parameters:

• module_name (str) – Name of the module to search in.

• nets (list[str]) – List of net names that must all appear on the instance.

• filter_regex (str | None) – Optional regular expression to filter the matched instance paths.

Returns:

List of hierarchical instance paths (strings).

find_instances_with_all_nets(module_name, nets) → list[str]

All nets must be on the instance.

Scan a Verilog netlist and return instance names inside module_name that have all nets in nets connected to any of their pins.

• Only looks at direct instances inside the given module (no hierarchy).

• Assumes gate-level style instantiations like

  cell_type inst_name (

  .A0(net1), .A1(net2), …

  );

Parameters:

• module_name (str) – Name of the module to search in.

• nets (list[str]) – List of net names that must all appear on the instance.

Returns:

List of instance names (strings).

Raises:

ValueError – If the specified module is not found in the netlist.

find_verilog_modules_regex(name_pattern) → list[str]

Find Verilog module names matching a regex pattern.

Parse a Verilog netlist and return all module names that match the given regex pattern.

Parameters:

name_pattern (str) – Regular expression pattern to match module names.

Returns:

List of module names matching the regex pattern.

get_instance_pins(hier_inst_path) → list[str]

Pin names connected to an instance.

Given a hierarchical instance path like: “Inst_LUT4AB_switch_matrix/inst_cus_mux161_buf_JE2BEG3” and a gate-level Verilog netlist, return a list of pin names connected to that instance, in the order they appear in the instantiation.

Parameters:

hier_inst_path (str) – Hierarchical instance path.

Returns:

List of pin names connected to the instance.

Raises:

• ValueError – If the top module or instance is not found in the netlist.

• RuntimeError – If an unexpected error occurs during hierarchy resolution.

get_module_instance_nets(module_name) → dict[str, list[str]]

Extract, for a module, all inst names and nets connected to each instance.

Parameters:

module_name (str) – Name of the module to inspect.

Returns:

Mapping: instance_name -> [net1, net2, net3, …] where each list contains all nets connected to that instance, order is the order of the pin connections in the instantiation.

Raises:

ValueError – If the specified module is not found in the Verilog source.

get_raw_verilog_netlist_data() → str

Return the raw Verilog netlist content as a string.

Returns:

The content of the Verilog netlist file.

nearest_port_from_pin(hier_pin_path, reverse=False, num_ports=1) → list[str]

Nearest port from pin.

Given a hierarchical pin path like “inst1/inst2/A0”, find the nearest top- level port connected to the same net as that pin. Depending on reverse, the search is done towards input ports (reverse=True) or output ports (reverse=False).

Parameters:

• hier_pin_path (str) – Hierarchical pin path.

• reverse (bool) – If True, search towards input ports; if False, towards output ports.

• num_ports (int) – Number of nearest ports to return. if less ports are found, return all found, which can be less than num_ports.

Returns:

Hierarchical paths of the nearest top-level ports.

Raises:

ValueError – If num_ports is less than 1.

nearest_ports_from_instance_pin_nets(inst_path, reverse=False, num_ports=1) → tuple[dict[str, list[str]], list[str]]

Nearest ports from instance pin nets.

Given a hierarchical instance path like “inst1/inst2”, find the nearest top- level ports connected to the same nets as the instance’s pins. Depending on reverse, the search is done towards input ports (reverse=True) or output ports (reverse=False).

Parameters:

• inst_path (str) – Hierarchical instance path.

• reverse (bool) – If True, search towards input ports; if False, towards output ports.

• num_ports (int) – Number of nearest ports to return per pin. if less ports are found, return all found, which can be less than num_ports.

Returns:

Mapping from instance net names to lists of nearest top-level port paths. The list is sorted starting from the nearest ports.

net_to_pin_paths_for_instance(hier_inst_path) → dict[str, str]

Paths from nets to hierarchical pins for an instance.

Given a hierarchical instance path like:

“Inst_LUT4AB_switch_matrix/inst_cus_mux161_buf_JE2BEG3”

and a gate-level Verilog netlist, return a mapping:

net_name -> “hier_inst_path/pin_name”

Only the leaf instance is resolved (no further hierarchy).

Example output:

{ “N1END2”: “Inst_LUT4AB_switch_matrix/inst_cus_mux161_buf_JE2BEG3/A0”, “N2END4”: “Inst_LUT4AB_switch_matrix/inst_cus_mux161_buf_JE2BEG3/A1”, … }

Parameters:

hier_inst_path (str) – Hierarchical instance path.

Returns:

Mapping from net names to pins keep hierarchy (no further hierarchy).

Raises:

• ValueError – If the top module or instance is not found in the netlist.

• RuntimeError – If an unexpected error occurs during hierarchy resolution.

net_to_pin_paths_for_instance_resolved(hier_inst_path) → dict[str, list[str]]

Resolve hierarchical instance pin paths to leaf pins.

Given a hierarchical instance path like: “Inst_LUT4AB_switch_matrix/inst_cus_mux161_buf_JE2BEG3” and a gate-level Verilog netlist, return a mapping: net_name -> [ “full_hier_pin_path1”, “full_hier_pin_path2”, … ] where each full hierarchical pin path is resolved down to leaf std-cell pins.

Parameters:

hier_inst_path (str) – Hierarchical instance path.

Returns:

Mapping from net names to lists of resolved leaf pin paths.

resolve_hier_pin(hier_pin_path) → list[str]

Resolve hierarchical pin path to leaf pins.

Parse a structural Verilog netlist and resolve a hierarchical pin path like “inst1/inst2/A0” down to all leaf std-cell pins connected to it.

Returns a list of hierarchical pin paths (strings).

Limitations

• Expects gate-level, structural Verilog: module/endmodule + simple instances

  of the form: CellType inst_name ( .PIN(net), … );

• Ignores assign statements, generate blocks, functions, etc.

• Assumes module port names are used as net names inside the module.

param hier_pin_path:

Hierarchical pin path in the format “inst1/inst2/pin”.

type hier_pin_path:

str

returns:

List of resolved leaf pin paths.

raises ValueError:

If the hierarchical pin path is invalid or if the top module or instances are not found.

raises KeyError:

If the target pin is not found on the last instance in the path.