bel

Basic Element of Logic (BEL) definition module.

This module contains the Bel class which represents a Basic Element of Logic in the FPGA fabric. BELs are the fundamental building blocks that can be placed and configured within tiles, such as LUTs, flip-flops, and other logic elements.

Classes

Bel

Information about a single BEL.

Module Contents

Bel

class Bel(src, prefix, module_name, internal, external, configPort, sharedPort, configBit, belMap, userCLK, ports_vectors, carry, localShared)[source]

Information about a single BEL.

The information is parsed from the directory of the BEL in the CSV definition file. There are some things to be noted:

  • The parsed name will contain the prefix of the bel.

  • The sharedPort attribute is a list of Tuples with the name of the port and IO information, which is not expanded out yet.

  • If a port is marked as both shared and external, the port is considered as shared, as a result, signals like UserCLK will be in the shared port list, but not in the external port list.

Parameters:

  • src (Path) – The source directory path of the BEL.

  • prefix (str) – The prefix of the BEL.

  • module_name (str) – The name of the module in the BEL.

  • internal (list[tuple[str, IO]]) – List of internal ports with their IO direction.

  • external (list[tuple[str, IO]]) – List of external ports with their IO direction.

  • configPort (list[tuple[str, IO]]) – List of configuration ports with their IO direction.

  • sharedPort (list[tuple[str, IO]]) – List of shared ports with their IO direction.

  • configBit (int) – The number of configuration bits of the BEL.

  • belMap (dict[str, dict]) – The feature map of the BEL.

  • userCLK (bool) – Whether the BEL has userCLK port.

  • ports_vectors (dict[str, dict[str, tuple[IO, int]]]) – Dictionary structure to save vectorized port information.

  • carry (dict[str, dict[IO, str]]) – Carry chains by name.

  • localShared (dict[str, tuple[str, IO]]) – Local shared ports of the BEL.

Variables:

  • src (Path) – The source directory of the BEL given in the CSV file.

  • prefix (str) – The prefix of the BEL given in the CSV file.

  • name (str) – The name of the BEL, extracted from the source directory.

  • module_name (str) – The name of the module in the bel. For verlog we can extract this from the RTL. For VHDL this is currently the same as name.

  • filetype (HDLType) – The file type of the BEL.

  • inputs (list[str]) – All the normal input ports of the BEL.

  • outputs (list[str]) – All the normal output ports of the BEL.

  • externalInput (list[str]) – All the external input ports of the BEL.

  • externalOutput (list[str]) – All the external output ports of the BEL.

  • configPort (list[tuple[str, IO]]) – All the config ports of the BEL.

  • sharedPort (list[tuple[str, IO]]) – All the shared ports of the BEL.

  • configBit (int) – The number of config bits of the BEL.

  • language (str) – Language of the BEL. Currently only VHDL and Verilog are supported.

  • belFeatureMap (dict[str, dict]) – The feature map of the BEL.

  • withUserCLK (bool) – Whether the BEL has userCLK port. Default is False.

  • ports_vectors (dict[str, dict[str, tuple[IO, int]]]) – Dict structure to save vectorized port information {<porttype>:{<portname>:(IO, <portwidth>)}}

  • carry (dict[str, dict[IO, str]]) – Carry chains by name. carry_name : {direction : port_name}

  • localShared (dict[str,tuple[str, IO]]) – {RESET/ENABLE,(portname, IO)} Local shared ports of the BEL. Are only shared in the Tile, not in the fabric.

Raises:

ValueError – If the file type is not recognized (not .sv, .v, .vhd, or .vhdl).