tile

Tile class definition for FPGA fabric representation.

Classes

Tile

Store information about a tile.

Module Contents

Tile

class Tile(name, ports, bels, tileDir, matrixDir, gen_ios, userCLK, configBit=0, pinOrderConfig=None)[source]

Store information about a tile.

Parameters:

  • name (str) – The name of the tile

  • ports (list[Port]) – List of ports for the tile

  • bels (list[Bel]) – List of Basic Elements of Logic (BELs) in the tile

  • tileDir (Path) – Directory path for the tile

  • matrixDir (Path) – Directory path for the tile matrix

  • gen_ios (list[Gen_IO]) – List of general I/O components

  • userCLK (bool) – True if the tile uses a clk signal

  • configBit (int, optional) – Number of configuration bits for the switch matrix. Default is 0.

  • pinOrderConfig (dict[Side, PinOrderConfig] | None, optional) – Configuration for pin ordering on each side of the tile. If None, defaults to BUS_MAJOR sorting on all sides.

Variables:

  • name (str) – The name of the tile

  • portsInfo (list[Port]) – The list of ports of the tile

  • bels (list[Bel]) – The list of BELs of the tile

  • matrixDir (Path) – The directory of the tile matrix

  • matrixConfigBits (int) – The number of config bits the tile switch matrix has

  • gen_ios (list[Gen_IO]) – The list of GEN_IOs of the tile

  • withUserCLK (bool) – Whether the tile has a userCLK port. Default is False.

  • wireList (list[Wire]) – The list of wires of the tile

  • tileDir (Path) – The path to the tile folder

  • partOfSuperTile (bool, optional) – Whether the tile is part of a super tile. Default is False.

  • pinOrderConfig (dict, optional) – Configuration for pin ordering on each side of the tile.

Properties

property globalConfigBits: int[source]

Get the total number of global configuration bits.

Calculates the sum of switch matrix configuration bits and all BEL configuration bits.

Methods

getEastPorts(io) → list[Port][source]

Get all ports with east wire direction filtered by I/O type.

Parameters:

io (IO) – The I/O direction to filter by (INPUT or OUTPUT).

Returns:

List of east-direction ports with specified I/O type, excluding NULL ports.

getEastSidePorts() → list[Port][source]

Get all ports physically located on the east side of the tile.

Returns:

List of ports on the east side, excluding NULL ports.

getNorthPorts(io) → list[Port][source]

Get all ports with north wire direction filtered by I/O type.

Parameters:

io (IO) – The I/O direction to filter by (INPUT or OUTPUT).

Returns:

List of north-direction ports with specified I/O type, excluding NULL ports.

getNorthSidePorts() → list[Port][source]

Get all ports physically located on the north side of the tile.

Returns:

List of ports on the north side, excluding NULL ports.

getSouthPorts(io) → list[Port][source]

Get all ports with south wire direction filtered by I/O type.

Parameters:

io (IO) – The I/O direction to filter by (INPUT or OUTPUT).

Returns:

List of south-direction ports with specified I/O type, excluding NULL ports.

getSouthSidePorts() → list[Port][source]

Get all ports physically located on the south side of the tile.

Returns:

List of ports on the south side, excluding NULL ports.

getTileInputNames() → list[str][source]

Get all input port destination names for the tile.

Returns:

List of destination names for input ports, excluding NULL and JUMP direction ports.

getTileOutputNames() → list[str][source]

Get all output port source names for the tile.

Returns:

List of source names for output ports, excluding NULL and JUMP direction ports.

getWestPorts(io) → list[Port][source]

Get all ports with west wire direction filtered by I/O type.

Parameters:

io (IO) – The I/O direction to filter by (INPUT or OUTPUT).

Returns:

List of west-direction ports with specified I/O type, excluding NULL ports.

getWestSidePorts() → list[Port][source]

Get all ports physically located on the west side of the tile.

Returns:

List of ports on the west side, excluding NULL ports.

get_min_die_area(x_pitch, y_pitch, x_pin_thickness_mult, y_pin_thickness_mult, x_spacing, y_spacing, frame_data_width=32, frame_strobe_width=20) → tuple[Decimal, Decimal][source]

Calculate minimum tile dimensions based on IO pin density.

For this tile, calculates the minimum physical width and height required to accommodate all IO pins at the PDK’s track pitch.

Parameters:

  • x_pitch (Decimal) – Horizontal pitch between tracks (DBU).

  • y_pitch (Decimal) – Vertical pitch between tracks (DBU).

  • x_pin_thickness_mult (Decimal) – Pin thickness multiplier in the horizontal direction.

  • y_pin_thickness_mult (Decimal) – Pin thickness multiplier in the vertical direction.

  • x_spacing (Decimal) – Pin spacing in the horizontal direction (DBU).

  • y_spacing (Decimal) – Pin spacing in the vertical direction (DBU).

  • frame_data_width (int, optional) – Frame data width, by default 32.

  • frame_strobe_width (int, optional) – Frame strobe width, by default 20.

Returns:

(min_width, min_height) where:

  • min_width: minimum width needed for north/south edge IO pins

  • min_height: minimum height needed for west/east edge IO pins

Notes

The minimum dimensions are calculated as:

  • min_width = max(north_pins, south_pins) * x_pitch

  • min_height = max(west_pins, east_pins) * y_pitch

These constraints prevent the NLP solver from suggesting dimensions that are physically impossible due to IO pin spacing requirements.

get_port_count(side) → int[source]

Count total number of expanded ports on a given side of the tile.

Parameters:

side (Side) – The side of the tile to count ports for.

Returns:

Total number of expanded ports on the given side.